1. Field of the Invention
This invention relates to an integrated circuit and, more particularly, to a metal oxide semiconductor ("MOS") circuit or method for providing current from a self cascode transistor arrangement having differing gate lengths to maximize output impedance and voltage swing from the circuit while minimizing voltage needed to operate the circuit.
2. Description of the Related Art
There are many techniques used to provide regulated current to a load circuit. One technique involves a current mirror. A conventional current mirror provides output current proportional to an input current. Separation between the input and output current ensures the output current can drive high impedance loads. Conventional current mirror designs have been implemented in both bipolar and MOS technology. MOS devices with short channel lengths and therefore faster operation have provided an impetus toward current mirrors based on MOS technology.
An important aspect in designing an MOS current mirror is to achieve optimum matching between the input (or "bias") current and the output current. Typically, the output current is designed to traverse a load placed across output terminals of the current mirror. The bias current is generally derived from a current source linked to a bias transistor. The bias transistor receives the bias current and produces a proportional bias voltage. The bias voltage is then placed on an output transistor configured to replicate (or "mirror") the bias current. Properly mirrored output current assumes the bias transistor and output transistor are fabricated with similar traits. For this reason, most modern day current mirrors are fabricated on a monolithic substrate as part of an integrated circuit.
FIG. 1 is a conventional current mirror 10 shown in simplistic form. A pair of MOS transistors Q1 and Q2 are shown having their gate terminals mutually connected, along with mutually connected source terminals. Since both transistors are fabricated on a monolithic substrate consistent with one another, the transistors operate in similar fashion. That is, transistors Q1 and Q2 can be n-type transistors or p-type transistors. Transistor Q1 is connected as a diode, whereby the gate terminal is shorted to the drain terminal.
The threshold voltage (Vt) of transistor Q1 is designed to be substantially the same as transistor Q2. Likewise, the voltage across the source and drain terminals (Von) of transistor Q1 when that transistor is in saturation is similar to Von across the source and drain terminals of transistor Q2. The bias current (Ibias) applied to transistor Q1 generates a bias voltage (Vbias) at the gate terminal of transistor Q1. Vbias is substantially equal to the threshold voltage (Vt) of transistor Q1, along with additional turn-on voltage (Von) required for current flow of Ibias. The relation between Von and Ibias is described in the following equations, and is sometimes referred to as the MOS square law relationship: EQU Ibias =K * W/L*(Vgs-Vt).sup.2,
where K is the MOS gain factor, W is the channel width, L is the channel length and Vgs is the gate-to-source voltage, and where EQU Von=Vgs-Vt,
which reduces to EQU Von=(Ibias/(K*W/L)).sup.1/2
Von is generally referred to as the saturation voltage of the transistor. If the drain-to-source voltage (Vds) of the transistor is larger than voltage Von, the transistor will operate in the "saturation"region. On the contrary, if Vds is lower than Von, the transistor will enter the "linear"region which, when entered, significantly degrades the gain and output impedance properties of the transistor.
In the instance shown, the diode-connection of transistor Q1 forces Vds of that transistor to be Vt+Von, which is larger than Von such that transistor Q1 is automatically placed in saturation. Whether transistor Q2 is in saturation or not depends on the drain voltage of node 12. The threshold voltage Vt of transistor Q1 is designed to be substantially the same as transistor Q2. Likewise, the Von of transistor Q1 is similar to Von of transistor Q2.
If transistors Q1 and Q2 in FIG. 1 have matched parameters (channel width, channel length, threshold voltage, etc.) current Ibias will be reproduced or mirrored through transistor Q2 as Iout. Furthermore, the mirrored current Iout will flow through whatever circuit is connected to output node 12. A circuit connected to output node 12 (interchangeably referred to as "Vout") is referred to as the load of the current mirror 10.
Proper design of a current mirror must take into account at least three important characteristics involved in all current mirrors. First, the output impedance as measured upon the output node must be as large as possible. If the output impedance between node 12 and a reference supply applied to node 14 is quite large, then changes in Vout will not substantially effect Iout. Thus, output impedance is often used to evaluate the stability of the current mirror. In the example shown in FIG. 1, output impedance is equal to the impedance across transistor Q2 and is inversely proportional to a channel length modulation factor .lambda. of that transistor, as follows: EQU Rout=R.sub.Q2 =1/(.lambda.*Iout)
A second parameter used in evaluating current mirrors is the output swing, or range, of Vout. At times when the load of the current mirror operates linearly the output swing measured at node 12 should be as high as possible to add to the robustness at which a load circuit can operate when connected to Vout. One edge of the output swing is limited by the saturation voltage (i.e., voltage to maintain saturation) of the load and/or transistor Q2. As defined above, the saturation voltage of transistor Q2 between the source and drain terminals is Von. The smaller the value of Von, the higher the output swing available to a load connected at node 12. In the example provided in FIG. 1, the saturation voltage of the load is equal to the saturation voltage Von of transistor Q2. It is desirable to minimize the saturation voltage Von of the output transistor Q2, and therefore to maximize the output swing available to a load device.
A third criteria involves the voltage required to operate the current mirror. This voltage is often referred to as the minimum operating voltage. The extent at which the operating voltage can be minimized is limited by the voltage required to bias the output transistor. Thus, in many cases, the minimum operating voltage is equal to Vbias. In the example of FIG. 1, the minimum operating voltage is Vt+Von. The three characteristics of a current mirror attributed to the exemplary circuit of FIG. 1 is shown below in reference Table I:
TABLE I ______________________________________ Output Impedance R.sub.Q2 Saturation Voltage Von Bias Voltage Vt + Von ______________________________________
The main disadvantage of current mirror 10 shown in FIG. 1 is the dependence between the output impedance and the channel length modulation factor .lambda. of transistor Q2. The channel length modulation factor will increase with shorter channel lengths. This means that the output impedance R.sub.Q2 will decrease with shorter channel lengths. As the densities of modern day integrated circuits increase, the channel lengths will decrease. Unfortunately, the trend toward higher density circuit devices will decrease the output impedance of current mirrors formed therefrom. In modern sub-micron processes, the effect of channel length modulation becomes significant. A single output transistor Q2 employed within a current mirror and having a channel length less than, e.g., 1.0 .mu.m will increase the output impedance to such an extent that the current mirror may be rendered useless in many applications. For example, if the output impedance is too small, DC gain will be deleteriously small if the current mirror is used as the load of an opamp.
In an effort to maintain high output impedance in submicron fabrication processes, many modern current mirrors employ a cascode arrangement. FIG. 2 illustrates a conventional cascode current mirror 18 having a cascode transistor Q4 inserted in series with transistor Q2, and cascode transistor Q3 added in series with transistor Q1. Transistor Q3 generates the bias voltage from Ibias necessary to replicate or mirror Ibias into the load device. Current mirror 18 has many features similar to current mirror 10, and therefore the similar features (i.e., output node 12 and reference voltage terminal 14, etc.) are identically numbered.
The cascode arrangement shown in FIG. 2 allows the voltage on the drain of transistor Q2 to be shielded from variations in Vout at node 12. Thus, the output impedance Rout of the load is increased by the gain of transistor Q4 as follows: EQU Rout=R.sub.Q2 (gm.sub.Q4 *R.sub.Q4)
Where gm.sub.Q4 and R.sub.Q4 represents the transconductance and output impedance, respectively, of transistor Q4. Since the product of gm.sub.Q4 and R.sub.Q4 is generally much larger than 1.0, the output impedance provided by circuit 18 is much greater than that provided by circuit 10. The disadvantage of a cascode current mirror is the reduced output swing and headroom due to the insertion of cascode transistors Q3 and Q4.
If Vt and Von of transistors Q3 and Q4 are identical, Vbias will be 2Vt+2Von, and the minimum Vout at node 12 will become Vt+2Von. The increased minimum Vout and Vbias makes the conventional cascode arrangement less desirable to low voltage circuits, or circuits which mandate minimal power consumption. Low voltage application implies the voltage swing of a load connected to node 12 must be maintained as large as possible. Consumption of that output swing and available headroom with an increase in the saturation voltage will prove detrimental to low voltage and/or power applications. Performance of cascode current mirror 18 is summarized in Table II as follows:
TABLE II ______________________________________ Output Impedance R.sub.Q2 (gm.sub.Q4 * R.sub.Q4) Saturation Voltage Vt + 2Von Bias Voltage 2Vt + 2Von ______________________________________
There have been numerous enhancements proposed to overcome the shortcomings of circuits 10 and 18. Specifically, those enhancements are derived in current mirrors having as high an output impedance as possible yet with minimal saturation and bias voltages. One example of a cascode current mirror with sufficiently high output impedance yet having minimal saturation voltage is illustrated in FIG. 3. Instead of using a single input current source and a pair of cascode bias transistors coupled to that single source, current mirror 22 of FIG. 3 uses two separate bias circuits. The separate bias transistors Q1 and Q3 are each coupled to receive current from a respective current source.
To more fully understand the differences between current mirrors 18 and 22, it is important to note how the gate and/or bias voltages upon output transistors Q2 and Q4 are derived. In circuit 18 shown in FIG. 2, the cascode-connected, bias transistors Ql and Q3 force the drain voltage of transistor Q3 to be at Vt+Von instead of Von. Thus, the drain terminal of transistor Q2 receives an extra threshold voltage V.sub.t necessary to maintain saturation of transistor Q2. Since saturation of transistor Q4 of circuit 18 requires the gate terminal to be above the source terminal by Vt and Von, the bias voltage at the gate terminal of transistor gate 4 is equal to (Vt+Von)+(Vt+Von)=2Vt+2Von. By employing an individual bias circuit for transistor Q4 in FIG. 3, the extra Vt at the drain of transistor Q2 can be omitted. If the channel width-to-channel length ratio (i.e., the "W/L" ratio) of transistor Q3 is 1/4 the W/L ratio of transistor Q1, then with the same Ibias current applied to both transistors Q1 and Q3, Vbias at the gate terminal of Q4 will be Vt+2Von. Since the drain voltage of transistor Q2 will be a sum of Vt and Von less than the bias voltage, the drain of transistor Q2 of circuit 22 will be merely Von. This will make the saturation voltage of circuit 22 at node 12 to be 2Von. This condition is usually referred to as the "high-swing condition". Note that the saturation voltage across the source and drain terminals of transistor Q4 remains as Von. If the drain voltage of transistor Q2 is merely Von, then the output voltage Vout is simply 2Von in circuit 22, rather than Vt+2Von in circuit 18.
Employing a lower Vout saturation voltage of 2Von in circuit 22 will afford a greater voltage swing of the load at node 12. Unfortunately, using two bias circuits and two separate current sources substantially increases the power dissipation within circuit 22, relative to a single bias cascode circuit 18. Accordingly, circuit 22 is not appropriate for low power applications. The following Table III summarizes the performance of circuit 22:
TABLE III ______________________________________ Output Impedance R.sub.Q2 (gm.sub.Q4 * R.sub.Q4) Saturation Voltage 2Von Bias Voltage Vt + 2Von ______________________________________
A circuit which avoids using separate bias circuits and high power consumption therewith is set forth in FIG. 4. Circuit 26 shown in FIG. 4 essentially divides a bias transistor Q3 into separate bias transistors Q3a and Q3b. Transistors Q3a and Q3b generate an intermediate voltage (bias voltage) at the source/drain connection point, that intermediate voltage being Vt+2Von. If the W/L ratios of transistors Q3b and Q3a are, for example, 1:1/3, then the gate voltage of transistor Q3b will be approximately 2Vt+3Von. Accordingly, intermediate voltage Vbias will become Vt+2Von which biases the load in a high swing condition. Transistor Q5 is inserted in the diode connection of transistor Q1 to equalize the drain voltage to transistor Q2 in order to achieve a more accurate current mirror. The disadvantage of circuit 26 is the rather large operating voltage input to transistors Q3a and Q3b, represented as 2Vt+3Von. The rather large bias voltage is not appropriate for low voltage applications. The performance parameters of circuit 26 is summarized in Table IV as follows:
TABLE IV ______________________________________ Output Impedance R.sub.Q2 (gm.sub.Q4 * R.sub.Q4) Saturation Voltage 2Von Bias Voltage 2Vt + 3Von ______________________________________
A current mirror which has a relatively high output voltage swing (small saturation voltage), but which uses only one current path or bias circuit is generally referred to as a "self cascode" current mirror. Current mirror 26 shown in FIG. 4 employs this self cascode arrangement, as does current mirror 30 shown in FIG. 5. Current mirror 30 is a somewhat simplified version of current mirror 26. Instead of bifurcating bias transistor Q3 into transistors Q3a and Q3b, a resistor 32 is provided. The resistance value of resistor 32 is chosen so that a voltage of Von across resistor 32 will occur. Von across resistor 32 will be added to Vt+Von generated by the gate of transistor Q1. Thus, the voltage applied to bias transistor Q4 will be approximately Von above Vt+Von. Circuit 30 can therefore achieve an output swing similar to circuit 22 without having to add an extra biasing circuit. The disadvantage of circuit 30 is that process variations will cause the resistance of resistor 32 to fluctuate. Any fluctuation whatsoever will replicate back to and be applied upon, the gate conductor of transistor Q4. Accordingly, both the saturation voltage and the bias voltage of circuit 30 are susceptible to variations in the semiconductor fabrication process. Performance parameters resulting from circuit 30 are listed in Table V as follows:
TABLE V ______________________________________ Output Impedance R.sub.Q2 (gm.sub.Q4 * R.sub.Q4) Saturation Voltage 2Von Bias Voltage Vt + 2Von ______________________________________
Circuit 34, shown in FIG. 6, presents an effort to produce a current mirror circuit which is less susceptible to semiconductor fabrication process variations, does not require a separate bias circuit, and maintains maximum output impedance. Current mirror circuit 34, similar to circuit 30, includes an output node 12 and a reference supply terminal 14. However, the transistors Q1, Q2, Q3 and Q4 are of either dissimilar type or have dissimilar thresholds. For example, transistors Q1 and Q2 can be enhancement-mode transistors, while transistors Q3 and Q4 are depletion-mode transistors. This implies that transistors Q3 and Q4 operate at negative thresholds. Alternatively, transistors Q3 and Q4 can be enhancement-mode transistors, yet operate at a lesser, albeit positive, threshold from that of transistors Q1 and Q2. The lower thresholds of enhancement-mode transistors Q3 and Q4 (e.g., 200 mv rather than, e.g., 400 mv), or the negative thresholds of depletion-mode transistors proves beneficial in a conventional setting. However, a description of depletion-mode operation in general is necessary to understand why depletion transistors have negative thresholds.
Opposite enhancement transistors, depletion transistors are normally "on" unless a gate-to-source voltage exceeding Vt occurs. In other words, a bias voltage on the gate electrode of depletion transistors is needed to deplete the channel region of majority carriers, and thus turn those transistors off. NMOS depletion-mode transistors require a negative gate voltage to be turned off while corresponding PMOS transistors require a positive gate voltage to be turned off.
An additional (or dissimilar) ion implantation step may be used to modify the threshold of one transistor from that of another, or to fabricate a depletion-mode transistor separate from enhancement-mode transistors. For example, in order for the required negative threshold voltage for a depletion-mode n-type MOS device to be produced, n-type impurities are implanted between the source and drain regions to form a built-in channel. The channel remains until the threshold voltage is exceeded in absolute value, thereby depleting a channel and terminating the saturation condition. Alternatively, to form a lower threshold transistor separate from, for example, a medium threshold transistor, the channel of a lower threshold transistor must be doped lighter than the medium threshold transistor, or a counter doping must be used. Ion implant is but one way to change thresholds among transistors, another way being, e.g., a change in gate oxide thickness or doping the gate conductor by a compensating amount.
Depletion transistors are said to have a threshold voltage Vt less than zero, and lower threshold transistors have a threshold voltage Vt less than medium threshold transistors. Accordingly, the depletion transistors or lower threshold transistors Q3 and Q4 are henceforth referred to as Vt2, whereas the threshold voltages of the medium threshold transistors Q1 and Q2 are henceforth referred to as Vt1. When transistors are "on", the saturation voltage across those transistors are equal and represented as Von. If all gates are tied together, as shown in FIG. 6, the saturation voltage seen at output node 12 will be Vt1-Vt2+Von, and the minimum operating voltage (bias voltage) is Vt1+Von. If Vt1 -Vt2=Von, the saturation voltage will become 2Von. Circuit 34 achieves lowest operating voltage equal to the single MOS current mirror of FIG. 1. Moreover, the saturation voltage produced at output node 12 of circuit 34 is comparably low, at least as small as many of the other conventional circuits described above. A summary of performance parameters for circuit 34 are listed in Table VI as follows:
TABLE VI ______________________________________ Output Impedance R.sub.Q2 (gm.sub.Q4 * R.sub.Q4) Saturation Voltage Vt1 - Vt2 + Von Bias Voltage Vt1 + Von ______________________________________
Unfortunately, circuit 34 requires additional processing steps to implement, e.g., the implant procedures needed to produce dissimilar threshold transistors or the depletion-mode transistors separate from the enhancement-mode transistors. For example, the depletion-mode transistors require a well region in which the respective depletion-mode transistor channels are formed separate from the channels of enhancement-mode transistors. Those well regions must be implanted or doped separate from dopants placed in the enhancement-mode transistor channels. Alternatively, a threshold adjust implant may be used to lessen (or enhance) threshold of one enhancement-mode transistor from that of another. In either instance, change in threshold or transistor type requires additional fabrication steps. If the additional implantation procedure is not carefully followed, contaminants will selectively arise in transistors employing the additional steps causing a skew in their performance relative to the transistors not having such steps. This skew may cause Von to differ from transistor to transistor. Moreover, contaminants or implant skewing may vary between transistors of dissimilar mode or threshold, causing a possible shift from a desired threshold performance.
It is imperative that the parameters used in producing transistors of a current mirror be carefully matched. Not only must the sizes of the bias and output transistors be controlled, but also the processing parameters used in forming the transistors must be consistent across the monolithic substrate. Implementing additional well regions, implant steps and photolithography sequences into the overall fabrication process may jeopardize the consistent performance needed to ensure accurate mirroring of the input bias current to a high impedance output current.